1. Field of the Invention
The present invention relates to a display driving system, and more particularly, to a display driving system using single level signaling with embedded clock signals, which includes a timing control section configured to embed a clock signal of the same level between data signals and transmit the signals to a panel driving section, and the panel driving section configured to recover the embedded clock signal from the transmitted data signals, sample data using the clock signal stabilized during a clock training interval and output image data, so that a data transmission speed is maximized, the level of signals to be transmitted and the frequency of the embedded clock signal are minimized, and impedance mismatch and EMI (electromagnetic interference) are suppressed to the minimum.
2. Description of the Related Art
These days, as the digital home appliance market is grown and the distribution of personal computers and portable communication terminals is increased, display devices as final output devices of home appliances and communication terminals are required to be light in weight and consume a small amount of power. Techniques for meeting these requirements are continuously proposed in the art. Accordingly, flat display devices, such as an LCD (liquid crystal display), a PDP (plasma display panel) and an GELD (organic electro-luminescence display), which replace the conventional CRT (cathode ray tube), have been developed and are being distributed.
Each of the flat display devices includes a timing controller which processes image data and generates a timing control signal so as to drive a panel used for displaying received image data, and column driving sections and row driving sections which drive the panel using the image data and the timing control signal transmitted from the timing controller.
In particular, recently, as display devices having a large screen size and a high resolution are demanded, a technique for transmitting data at a high speed from the timing controller to the column driving sections is required. In this regard, since electromagnetic interference (EMI) is caused by electromagnetic waves while transmitting data at a high speed, the level of a signal to be transmitted has been considerably decreased.
Under these situations, differential signal transmission schemes capable of reducing electromagnetic interference (EMI) and transmitting data at a high speed, such as mini-LVDS (low voltage differential signaling) and RSDS (reduced swing differential signaling), have been increasingly used.
FIG. 1 is a view illustrating transmission of data differential signals and clock differential signals in conventional LVDS, and FIG. 2 is a view illustrating transmission of data differential signals and clock differential signals in conventional RSDS.
Referring to FIGS. 1 and 2, the recently used mini-LVDS or RSDS has at least one data differential signal line which is connected to a timing controller 10 so as to support a desired bandwidth and a separate clock differential signal line which is configured to output a clock differential signal in synchronism with a data differential signal, and adopts a multi-drop scheme in which respective column driving sections 20 share the data differential signal line and the clock differential signal line.
While the multi-drop scheme has advantages in that the timing controller 10 can be used irrespective of the number of outputs depending upon a resolution, that is, the number of the column driving sections 20, it encounters a problem in that signal distortion by reflection waves is caused and electromagnetic interference (EMI) increases due to impedance mismatch occurring at points where the data differential signal and the clock differential signal are supplied to the respective column driving sections 20, and in that an operation speed is limited due to a large load applied to the clock differential signal.
In order to overcome the problem caused in the multi-drop scheme, PPDS (point-to-point differential signaling), in which data differential signals are separately supplied to respective column driving sections and a clock differential signal is shared by the column driving sections, has been proposed in the art.
FIG. 3 is a view illustrating transmission of data differential signals through independent data signal lines in conventional PPDS, and FIG. 4 is a view illustrating chain type transmission of clock differential signals in another conventional PPDS.
Referring to FIG. 3, in PPDS, an independent data line is formed between a timing controller 10 and each column driving section 20 so that data differential signals are separately supplied to respective column driving sections 20. Therefore, impedance mismatch, electromagnetic interference (EMI) and overloading of a clock differential signal that can otherwise be caused in the multi-drop scheme can be overcome.
In the PPDS, the clock differential signal should be transmitted at a high speed. In this regard, because the PPDS shown in FIG. 3 is configured to share the clock differential signal, an operation speed is limited when a load applied to the clock differential signal is substantial. Hence, as shown in FIG. 4, a signal transmission scheme is used, in which a clock differential signal is supplied to the respective column driving sections 20 in a chain type. In this case, a problem is caused in that sampling of data is not properly implemented due to clock delay occurring between the column driving sections 20.
Further, as display devices trend toward a large screen size and a high resolution and the number of column driving sections increases accordingly, the PPDS scheme encounters a problem in that the numbers of data and clock signal lines increase at the same rate, connection of entire signal lines is complicated, and a high manufacturing cost results.
FIG. 5 is a view illustrating a conventional AiPi (advanced intra-panel interface).
Referring to FIG. 5, the AiPi has recently been suggested in which data and clock signals are distinguished by multi-levels and data differential signals with clock signals embedded therebetween are transmitted from a timing controller to column driving sections through independent respective signal lines. Therefore, the number of signal lines can be significantly decreased, and electromagnetic interference (EMI) is reduced. Also, since the operation speed and the resolution of a panel are increased despite the decrease in the number of signal lines, it is possible to solve the problems caused by skew or jitter occurring between the data and clock signals while transmitting signals at a high speed.
As a consequence, as described above, in the multi-drop scheme such as the conventional mini-LVDS and RSDS for transmitting data at a high speed from the timing controller to the column driving sections, a problem is caused in that impedance mismatch and overloading of the signal line for transmitting the clock differential signal occur. In the conventional PPDS, while data differential signals and clock differential signals are separately supplied to respective column driving sections so as to overcome the problem caused in the multi-drop scheme, as display devices trend toward a large screen size and a high resolution, the number of signal lines increases compared to the multi-drop scheme, whereby the complexity of signal lines for connecting the timing controller and the column driving sections is increased and a lot of costs is incurred.
Moreover, in the recently proposed AiPi transmission scheme, while signals are transmitted by embedding clock signals between data to decrease the number of signal lines and prevent the occurrence of skew between the data and clock signals, since the embedded clock signals are transmitted to constitute multi-level signals by having a level greater or less than data signals, problems are caused in that it is impossible to minimize the level of signals to be transmitted and reduction of electromagnetic interference (EMI) is poor.
As a consequence, an interface for transmitting data at a high speed between a timing controller and column driving sections, which can decrease the number of signal lines for transmitting data differential signals and clock differential signals, minimize electromagnetic interference (EMI), and prevent the occurrence of skew and jitter between signal lines, is keenly demanded in the art.